1. Field of the Disclosure
The present disclosure relates to hierarchical architecture of testing circuits for testing of an integrated circuit using automated test equipment (ATE).
2. Description of the Related Art
A defect is an error introduced into an integrated circuit (IC) during a semiconductor manufacturing process. Defects that alter the behavior of the IC can be described by a mathematical fault model. During testing of the IC, a test pattern is applied to the IC and logic value outputs from the IC are observed. When the IC is operating as designed, the logic value output coincides with expected output values specified in test patterns. A fault in the IC is detected when the logic value output is different than the expected output.
Automatic Test Pattern Generation (ATPG) refers to an electronic design automation (EDA) process that generates a set of test patterns for applying to an IC to detect faulty behavior caused by defects in the IC. The generated patterns are used to test semiconductor devices after manufacture, and in some cases to assist with determining the cause of fault. The fault model may be used to generate the test patterns that effectively covers certain types of faults with a fewer number of test patterns.
To receive and detect faults in the IC, the IC includes a test circuit that receives and applies the test patterns to one or more scan chains. A scan chain includes a row of multiple scan flops that output a certain logic value when the test pattern is applied. An unexpected output of a scan flop is indicative of certain faults or defects in circuit components associated with the scan flop. Outputs of multiple scan flops may be compressed into a bit stream to reduce data bandwidth and pins associated with the testing of IC.
As the number of circuits integrated on a System-on-a-Chip (SOC) increases, building a hierarchical test infrastructure is becoming more important. An efficient hierarchical design-for-test (DFT) implementation not only enables quality testing of the SOC but also provides a tool that can aid debugging the problems in the integrated circuit during manufacturing. With the evolution of compression technologies in the recent years, more and more people are migrating away from scan methodology for manufacturing test to save test cost and test time.